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-neural-network-compression-and-accelerator-on-hardware

My name is Fang Biao. I'm currently pursuing my Master degree with the college of Computer Science and Engineering, Si Chuan University, Cheng Du, China. For more informantion about me and my research, you can go to [my homepage](https://github.com/hisrg). One of my research interests is architecture design for deep learning and neuromorphic computing. This is an exciting field where fresh ideas come out every day, so I'm collecting works on related topics. Welcome to join us!

accelerating-quantized-cnn-inference-on-fpga

Accelerating-Quantized-CNN-Inference-on-FPGA(RTL)

ai-job-notes

AI算法岗求职攻略（涵盖准备攻略、刷题指南、内推和AI公司清单等资料）

avsdadc_3v3

This repository will maintain simulation files, layout files and other relevant files on the SAR ADC worked on in the VSD Summer Online Internship 2020 by the ADC Team.

awesome-approximate-dnn

Curated content for DNN approximation, acceleration ... with a focus on hardware accelerator and deployment

awesome-automl-papers

A curated list of automated machine learning papers, articles, tutorials, slides and projects

blog

cardetectionzyboz720

cnn_dpr

Landmark Detection with CNN on FPGA including DPR

cnn_for_slr

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

conv_arithmetic

A technical report on convolution arithmetic in the context of deep learning

convnerf

[ICCP 2021] ConvNeRF, a novel scheme to generate opacity radiance fields with a convolutional neural renderer for fuzzy objects with high feaqurncy details.

de2

Verilog code for the Altera DE2 Board

deep-neural-network-hardware-accelerator

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

deeppyramid

Deep feature pyramids for various computer vision algorithms (DPMs, pyramid R-CNN, etc.)

deploying_cnn_on_fpga_using_opencl

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

detectron2

Detectron2 is FAIR's next-generation research platform for object detection and segmentation.

digital-flow

This is a tutorial on standard digital design flow

dnn-hardware-accelerator

SystemVerilog files for lab project on a DNN hardware accelerator

dnn_accelerator

Complete design (RTL, testbenches, etc.) and synthesis/layout files for a convolutional neural network hardware accelerator.

dp-dpm

ee046211-deep-learning

Jupyter Notebook tutorials for EE 046211 Deep Learning course at the Technion

ee272a_dnn_accelerator

Implementation of a DNN accelerator Hardware using Resnet_18 architecture

embodiedqa

Train embodied agents that can answer questions in environments

exercises-solutions

C, C++ and Python Code for Exercises and Solutions

eyerissf

An Eyeriss Chip (researched by MIT, a CNN accelerator) simulator and New DNN framework "Hive"

facedetectionfpga

fcniris

A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional Networks

featurereductiongenetic

Feature reduction using genetic algorithm

fishy-stuff