stativeboss Goto Github PK

1x3_router

blog_site

csv-populator-gui

development-of-a-matrix-multiplication-unit-using-2d-systolic-array-architecture

digitalgarden

enabling-sdc-swithces-in-yosys

for_ref_delete

This is a 5-day workshop on RTL Design and Synthesis using open source tools for logic design, simulation, synthesis and technology mapping with Sky130 PDK. (iVerilog, GTKwave, Yosys and Sky130 technology)

for_reference

This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primarily focused on a complete FPGA flow using the maximum open-source tools.

fpga-fabric_design_and_architecture

An intensive 5-day workshop organized by VLSI System Design

mips32

poole

The Jekyll Butler. A no frills responsive Jekyll blog theme.

sky130_rtldsn_wrkshp

My notes on RTL design in Verilog using SKY130 PDK

static_timing_analysis

stativeboss.github.io

Build a Jekyll blog in minutes, without touching the command line.

verilog-pcie

Verilog PCI express components