When multiple producers connect to a single consumer, there needs to be some synchroni

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Multiple producer synchronization about halide-to-hardware HOT 5 OPEN

jeffsetter commented on August 17, 2024

Multiple producer synchronization

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jeffsetter commented on August 17, 2024

One solution is to make both have the same number of iterations.

Another solution is to connect a valid signal to the ren of the other producer.

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dillonhuff commented on August 17, 2024

@jeffsetter maybe I'm misunderstanding, but isn't it the responsibility of the user to insert delays (using the fifo_depth scheduling directive) that synchronize the arrival times of data from different producers?

Is there a specific app where I could see an example of this problem?

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jeffsetter commented on August 17, 2024

That is the case when linebuffers are used (which inherently must have some delay due to internal registers). My assumption for ROM is that there is zero delay. In fact, this is not correct, it takes a cycle, and so the thinking is the mapper will synchronize the arrival times with the actual timing.

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dillonhuff commented on August 17, 2024

I think I understand. In the new CoreIR code generator I have added delay balancing for kernels with different latencies (for example because one uses a ROM and the other is all combinational logic).

Here is a test case for such a situation:

Halide-to-Hardware/apps/hardware_benchmarks/tests/merged_unit_tests/test_main.cpp

Lines 2544 to 2597 in 71f972a

    
           void different_latency_kernels_test() { 
        
             ImageParam input(type_of<uint8_t>(), 2); 
        
             ImageParam output(type_of<uint8_t>(), 2); 
        
             Var x("x"), y("y"); 
        
             Var xi, yi, xo, yo; 
        
             Func lut("lut"); 
        
             Func translated("kernel"); 
        
             Func brightened("brightened"); 
        
             Func diff("diff"); 
        
             Func hw_input("hw_input"); 
        
             Func hw_output("hw_output"); 
        
             hw_input(x, y) = cast<uint8_t>(input(x, y)); 
        
             lut(x) = cast<uint8_t>(Expr(x)); 
        
             translated(x, y) = lut(hw_input(x, y)); 
        
             brightened(x, y) = hw_input(x, y) + 10; 
        
             diff(x, y) = brightened(x, y) - translated(x, y); 
        
             hw_output(x, y) = diff(x, y); 
        
             int outTileSize = 5; 
        
             Halide::Buffer<uint8_t> inputBuf(outTileSize, outTileSize); 
        
             Halide::Runtime::Buffer<uint8_t> hwInputBuf(inputBuf.width(), inputBuf.height(), 1); 
        
             indexTestPatternRandom(inputBuf, hwInputBuf); 
        
             Halide::Runtime::Buffer<uint8_t> outputBuf(outTileSize, outTileSize); 
        
             auto cpuOutput = realizeCPU(hw_output, input, inputBuf, outputBuf); 
        
             printBuffer(cpuOutput, cout); 
        
             hw_output.compute_root(); 
        
             hw_input.compute_root(); 
        
             hw_output.tile(x, y, xo, yo, xi, yi, outTileSize, outTileSize) 
        
               .reorder(xi, yi, xo, yo); 
        
             lut.compute_at(hw_output, xo).unroll(x); 
        
             translated.linebuffer(); 
        
             brightened.linebuffer(); 
        
             diff.linebuffer(); 
        
             hw_input.stream_to_accelerator(); 
        
             hw_output.hw_accelerate(xi, xo); 
        
             hw_output.print_loop_nest(); 
        
             auto context = hwContext(); 
        
             vector<Argument> args{input}; 
        
             auto m = buildModule(context, "hw_different_latencies", args, "different_latencies", hw_output); 
        
             string accelName = getInputAlias("accel_interface_info.json"); 
        
             runHWKernel(accelName, m, hwInputBuf, outputBuf); 
        
             compare_buffers(outputBuf, cpuOutput); 
        
             PRINT_PASSED("Different latency kernels"); 
        
           }

Is this the kind of thing you are talking about or am I misunderstanding the problem?

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jeffsetter commented on August 17, 2024

This is actually dynamic instead of just static latency between producers. For example, a producer might treat the edges differently from the other.

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Multiple producer synchronization about halide-to-hardware HOT 5 OPEN

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	void different_latency_kernels_test() {
	ImageParam input(type_of<uint8_t>(), 2);
	ImageParam output(type_of<uint8_t>(), 2);

	Var x("x"), y("y");
	Var xi, yi, xo, yo;

	Func lut("lut");
	Func translated("kernel");
	Func brightened("brightened");
	Func diff("diff");
	Func hw_input("hw_input");
	Func hw_output("hw_output");

	hw_input(x, y) = cast<uint8_t>(input(x, y));
	lut(x) = cast<uint8_t>(Expr(x));
	translated(x, y) = lut(hw_input(x, y));
	brightened(x, y) = hw_input(x, y) + 10;
	diff(x, y) = brightened(x, y) - translated(x, y);
	hw_output(x, y) = diff(x, y);

	int outTileSize = 5;
	Halide::Buffer<uint8_t> inputBuf(outTileSize, outTileSize);
	Halide::Runtime::Buffer<uint8_t> hwInputBuf(inputBuf.width(), inputBuf.height(), 1);
	indexTestPatternRandom(inputBuf, hwInputBuf);
	Halide::Runtime::Buffer<uint8_t> outputBuf(outTileSize, outTileSize);
	auto cpuOutput = realizeCPU(hw_output, input, inputBuf, outputBuf);

	printBuffer(cpuOutput, cout);
	hw_output.compute_root();
	hw_input.compute_root();

	hw_output.tile(x, y, xo, yo, xi, yi, outTileSize, outTileSize)
	.reorder(xi, yi, xo, yo);

	lut.compute_at(hw_output, xo).unroll(x);
	translated.linebuffer();
	brightened.linebuffer();
	diff.linebuffer();
	hw_input.stream_to_accelerator();
	hw_output.hw_accelerate(xi, xo);

	hw_output.print_loop_nest();

	auto context = hwContext();
	vector<Argument> args{input};
	auto m = buildModule(context, "hw_different_latencies", args, "different_latencies", hw_output);

	string accelName = getInputAlias("accel_interface_info.json");

	runHWKernel(accelName, m, hwInputBuf, outputBuf);
	compare_buffers(outputBuf, cpuOutput);
	PRINT_PASSED("Different latency kernels");
	}