Comments (2)
Dolu1990
commented on May 10, 2024
Actualy, only a vhdl testbench without stimulus is automaticly generated. I don't have explore this way so much to keep focus on RTL, but it's true that it could be very usefull to have a way to simply test the generated hardware, which is realy borring in vhdl.
Probably solution like cocotb are very good one (Drive DUT from software world)
Having something like it in Scala could be greate, and then open the door to implement DSL (as your proposal)
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Dolu1990
commented on May 10, 2024
♪ lolilol ♫
http://spinalhdl.github.io/SpinalDoc/spinal/sim/example/single_clock_fifo/
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Related Issues (20)
- SimMutex locked repeatly crashes the simulation HOT 5
- Checking for unknown values in simulation HOT 1
- JTAG VPI Simulation gets blocked by IO HOT 2
- Dump ports of `Mem` in FST waveforms? HOT 3
- HDElkDiagram generated html could not be convert ed to image using wkhtmltoimage correctly HOT 1
- Qsysify and Axi4: incorrect _hw.tcl generation HOT 1
- Could not load XSI simulation shared library HOT 1
- Blackboxing RAM with one read and one readWrite port HOT 2
- Performance of PriorityMux HOT 18
- Redundant Flow API Calls. HOT 4
- Parallel test execution in SpinalSim? HOT 5
- Are there some bugs in clockDomain.waitSampling() API? HOT 10
- Is there a "DONT_TOUCH" attribute for Components in Spinal ? HOT 2
- Unknown reason for hierarchy violation HOT 4
- Slower on the intranet network HOT 9
- Support for memories with read latency higher than 1 HOT 18
- Can't infer width of Payload HOT 2
- Seed does not work at parallel test of spinal sim HOT 2
- Underscore in literals HOT 3
- Linux: Spaces in path break formal verification HOT 7
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