I tried running the ulp directly from the .brd file in Eagle. Initially I get a complaint that the script doesn't know what board color to use, but after that it seems to run quietly. But I can't find the result.
It does create a folder "Production" in my project folder with a file "ordering_instructions", but that's all it does. I get no error message, not notification that it did the job or where to look for results.
Can you help. My Eagle version is 9.5.2.

BTW:

1. against better judgement, Eagle is installed in C:\EAGLE 9.5.2. My preference would be to put in in the "Program Files (x86)", but I kept the default installer setting to avoid the risk for issues with wrong paths.
2. related to this, the ulp script fails to find "C:\Eagle.ulp". Not sure which part of the program is generating this error (Eagle .exe or the sparkfun ulp), but it doesn't make sense to have an ulp file in the root directory. I looked for eagle.ulp in the Eagle 9.5.2 program folder (and subfolders). It doesn't seem to exist at all. I looked for the string "Eagle.ulp" in the panelizer ulp, but drew a blank as well.

When exposing the card edge of a board in the panelizer, it rotates the board around so the card edge faces up, however it doesn't rotate the text objects in copper such as layer numbers correctly.

Need to add .txt.* to zip process.

Hi
I just installed Eagle 8.2.2 and tried to use the setup scripts. It seems to fail due to the spaces in the Eagle directory name. I tired to install Eagle to another directory but they do not allow that.
After the install the eagle.scr fails as well. It shows up as not found

C:/EAGLE 8.2.2/scr/eagle.scr, Line 36:

Can't find 'C:\EAGLE.scr'

Note that the directory is also not correct.

I am trying the SparkFun-CAMmer.ulp but get a Error: Command failed. message.
Not sure if this it due to me placing the content of the SparkFun_Eagle_Settings folder in the wrong locations or if it is due to this only working on Windows and Linux.

Thanks for your help and for making all these great tools available to the public.

We should think about changing the layerSetup in SparkFun-4-layer-PCBWAY-LIMIT.dru. It is currently set to:

• layerSetup = ([15:(1*2)+15*16])

which makes it possible to define blind vias between layers 1&2 and 1&2&15.

Maybe that's as intended, but it seems a weird choice. I got caught out by this when I accidentally defined a 1&2&15 via for one of my layer 15 signal traces. Unsurprisingly, there was a bad joint between the trace and via as the board was fab'd as a standard 4-layer board.

The other 4-layer .dru's use:

• layerSetup = ((1*2)+(15*16))
• layerSetup = (1*2*15*16)
• layerSetup = (1+2*15+16)

I noticed this issue while panelizing the board below. It is supposed to have drill holes to interface with a TFT display but these were dropped when panelizing. I believe this is due to the fact that the drill holes are part of a footprint that has its origin outside of the "active" board area (within dimension lines).

A solution to this problem will require (at least):

• Additionally including in the copy group components whose origin is outside the active board area AND have an "effect" on the board.
• Continuing to disregard "non-hardware" items like the CC note and attributions so as to reduce clutter.
• Continuing to capture items on all applicable layers

The original quote was ambiguous so we are erring on the side of caution.

I tried to load "SparkFun-2-layer-STANDARD.dru" into Eagle 8.3.2, it didn't load and gave the error: "Parse error in design rules File" (directory) "line 1".

Can you please help I would like to submit a board to be made in the next few days.

Hello guys I noticed for the panelizer ULP there seems to be an issue when i just use a circle as outline for the board, lines are working no problem, but full closed circles seem that are not able to be panelized.

Thanx for the amazing work :)

I have been using the panelizer.ulp version from Jan/21 with no problemas. Since I update to current version, I can't creat a panel, it crashes. It also has a bug if you choose dimensions in milimeter. Thank you in advance.

Hello guys, just another quick doubt, I actually have used the panelizer several months now, but I recently changed from pcb manufacturer and are kinda stricter, so I have already noticed that some labels get replaced by increments in numbers like R1 gets like R11 R12 etc, resulting in different designs, what is the correct option to avoid this?

thank you

Note, this is a slightly strange use case. I am using both inner layers for GND polygons, and they do not have any traces on them. They are simply being used to help sink heat.

It seems that the "hasFourLayers()" function is not catching them, due to the fact that my inner layers do not have traces.

For a quick fix, I added some "dummy" traces (actually just wires drawn on the inner layer with net names that don't cause air-wires).

This totally works, but I thought I'd throw this up here, just in case someone else runs into it, and maybe might have a more creative way to solve this - on the ULP end.

For reference, this is what I did with my inner GND layers (They have the text objects "2" and "3" in this screenshot):

tried a few ULP like BOM generator and I just get script errors. Useless!