Name: Syed Soobaan Mohiuddin Quadri
Type: User
Company: Elveego Circuits Pvt. Ltd.
Bio: Design and Verification Engineer, Specialized in Verilog, SystemVerilog, UVM Methodology
Location: Bengaluru, India.
Blog: Soobaan
Syed Soobaan Mohiuddin Quadri's Projects
100 Days of RTL
finding the Absolute Value
AHB to APB Bridge VIP
System Verilog and Emulation. Written all the five channels.
An FPGA implementation of Cummings' Asynchronous FIFO
A curated list of awesome warez and piracy links
CIC-filter core
The Ultra-Low Power RISC Core
The Ultra-Low Power RISC-V Core
Focus on prompting and generating
OpenSource HummingBird RISC-V Software Development Kit
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
A 32-bit RISC-V soft processor
RISC-V Cores, SoC platforms and SoCs
RISC-V Formal Verification Framework
A very simple and easy to understand RISC-V core.
UART design in SV and verification using UVM and SV
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.