sikeclown Goto Github PK
Name: Chaitanya Kunda
Type: User
Bio: I'm Chaitanya, a recent graduate from SNU, Noida. Working as a FPGA Engineer for low latency trading systems
Location: Hyderabad
Chaitanya Kunda's Projects
100-days-of-rtl
This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools
100daysofrtl
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
my_rtl
my_rtl_designs
rtl
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