Sat J. Patel's Projects
Verilog HDL code for 4x4 multiplier
C++ implementation of a 128-bit AES encryption/decryption tool.
An SV implementation of Asynchronous FIFO
A Verilog HDL Code for an automatic food cooker
Done as a part of CSE-614: Computer Architecture
My seminar topic as a part of BTech course in ECE. I would be first implementing different schemes of frequency domain watermark embedding and then implement the best one on FPGA.
All impirtant Data Structures for coding in Python
RTL Design and Verification - with AXI-Lite Compatible Memory
Useful MATLAB Codes
A generic FIR filter implementation in System Verilog, and verified with Cocotb
FP16_Arithmetic modules designed by Verilog and VHDL
Smart Class Projector Ecosystem - Swadeshi Microprocessor Challenge
Done as a part of coursework for ECEN-676 (Advanced Computer Architecture) at Texas A&M, Spring 2023
A Verilog HDL Code for an Intelligent Traffic Light Control System ( Using State Machines)
Google IT Automation with Python Professional Certificate - Practice files
Basic implementation of MIPS32
An initial proof of concept for neural network on FPGA
A repo for a Program and Data Representation university-level course
A Verilog Code to mimic the functionality of the 8255 Interfacing Integrated Circuit
SV Implementation of RISC V ISA
Config files for my GitHub profile.
A Tic Tac Toe game
Contains all my written technical articles
A C++ Implementation of Tomasulo's Algorithm
UVM Practice on my own on a Small ALU
Useful Verilog HDL Codes which can be used in multiple design systems.
Over the course of my learning, I made some simple but useful VHDL codes, which can be helpful for bigger, more complex projects, and for those who are just beginning in the world of VHDL.
A small, light weight, RISC CPU soft core