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rithwik10's Projects

franka_ros icon franka_ros

ROS integration for Franka Emika research robots

mips_pipelined_cpu_verilogmodel icon mips_pipelined_cpu_verilogmodel

A multi-cycle pipelined processor capable of performing basic ALU and branch instructions. The design incorporates a hazard detection unit to tackle the possible data and control hazards. Verilog is used as the HDL to define the RTL modules. Block design and testbench simulations are done in Xilinx Vivado.

opencv-course icon opencv-course

Learn OpenCV in 4 Hours - Code used in my Python and OpenCV course on freeCodeCamp.

romanov_simulation icon romanov_simulation

This repository consists of resources and work done in the simulation and mechanical aspect of RoManOV.

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