expr: explicit SIMD about risinglight HOT 7 OPEN

Bounds checking does not allow the compiler to auto-vectorize.

Try and test
res = vec::from_iter(a.iter().zip(b.iter()).map())

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https://matklad.github.io/2023/04/09/can-you-trust-a-compiler-to-optimize-your-code.html

:p

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yeah it works! https://godbolt.org/z/eG61feTM4 I'll check if binary operations are actually vectorized in RisingLight later...

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You can check them via cargo bench --bench array. It would be obvious which operations are vectorized and which are not.

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I still prefer auto-vectorization over explicit SIMD, because usually compilers do it better than humans and it makes code cleaner. However, as mentioned above, auto-vectorization requires special craft of codes. There are plenty of things that prevent SIMD, e.g. bound check, branching. AFAIK, there's also no way to hint or ensure auto-vectorization for a piece of code in Rust, i.e. no equivalent for #pragma clang loop vectorize(enable).

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Yep, I also think auto vectorization

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… is good

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