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Name: Riccardo Fontanini
Type: User
Bio: I'm an electronic engineer graduated at University of Udine. Now I'm attending the 2nd level (Master degree) course of electronic engineering.
Name: Riccardo Fontanini
Type: User
Bio: I'm an electronic engineer graduated at University of Udine. Now I'm attending the 2nd level (Master degree) course of electronic engineering.
Implementation of AES encryption standard 128, 192 and 256 bits based on AES paper, "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard and "An ASIC Implementation of the AES SBoxes" article of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger
Aes implementation in C with dynamic SBOX
Cap protocol implementation in C for comunicate with FPGA for AES project
Dynamic SBOX in VHDL, based on "An ASIC Implementation of the AES SBoxes" article of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger
AES encryption standard 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard and "An ASIC Implementation of the AES SBoxes" of Johannes Wolkerstorfer, Elisabeth Oswald, and Mario Lamberger
Analysis of book dataset, and created a server based application to show result of this analysis
Datacell implementation of AES encryption standard 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard
Data unit of AES 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard
EDC Example Projects
Simple example of CNN with tensorflow
Key generator of AES 128, 192 and 256 bits based on AES paper and "A Highly Regular and Scalable AES Hardware Architecture" article of Stefan Mangard
MIPS Implementation on VHDL
Simple parallel architecture implementations
Exercise of pressbutton
Client - Server application for information security
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Open source projects and samples from Microsoft.
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Data-Driven Documents codes.
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