Comments (2)
niwis
commented on August 13, 2024
Reverting the UART to the Xilinx UART solves the issue. Most likely it is a hardware bug in the apb_uart_sv. (It could also be a SW issue with the memory/interrupt map. But I triple-checked everything I am aware of).
I will attach an ILA to the apb_uart_sv's interface to better understand the problem.
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niwis
commented on August 13, 2024
The apb_uart_sv is broken. Some potential issues:
- CTS tied to
0 - MS interrupt not cleared on MS register read
- ...
We are replacing the apb_uart_sv with a new SV version of apb_uart in #295.
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