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aes

VHDL design of an AES cryptographic function. Compliant with FIPS 197. Currently supports AES-256. With test benches and demonstration projects.

grlib-gpl-2020.2-b4254

Adding support for LEON3 - LEON5 - NOELV on terasic DE10 nano and DE0 nano boards

grlib_leon_1

library with leon 1 core

grlib_leon_2

library with leon 2 core

intel_cyclone_v_soc

Collection of examples using the intel Cyclone 5 SOC FPGA. Demonstrated on Terasic DE10-nano board

neorv32

:desktop_computer: A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

provoostkris

Config files for my GitHub profile.

provoostkris.github.io

spacewirecodecip_100mhz

vhdl-axis-uart

UART to AXI Stream interface written in VHDL

vhdl-hdmi-out

HDMI Out VHDL code , updated to support low cost terrasic FPGA boards

vlink

RTL descriptions and test benches for a virtual link

xilinx_zynq

Collection of Xilinx ZynQ examples. Examples using PL, PS or both. Demonstrated on a QMTECH ZYNQ 7010 board