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ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

berkeley-hardfloat

bextdep

Reference Hardware Implementations of Bit Extract/Deposit Instructions

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-wrapper

Wrapper for ETH Ariane Core

gem5

The official repository for the gem5 computer-system architecture simulator.

hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

linux

Linux kernel source tree

open-source-network-on-chip-router-rtl

openc910

OpenXuantie - OpenC910 Core

qemu

Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

ravenoc

RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-ocelot

Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

rocket-chip

Rocket Chip Generator

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

tnoc

Network on Chip Implementation written in SytemVerilog

verilator

Verilator open-source SystemVerilog simulator and lint system

xiangshan

Open-source high-performance RISC-V processor

xv6-riscv

Xv6 for RISC-V

xvisor-next

Xvisor: eXtensible Versatile hypervISOR