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aes

aesgen

A python based AES core generator

awesome-opensource-asic-resources

basic-oop-testbench

comm_systems_labs

cppnd-memory-management-chatbot

cppnd-program-a-concurrent-traffic-simulation

The final project for the Udacity C++ Nanodegree Concurrency course

cppnd-system-monitor

Student repository for the CppND OOP course project

cyyrv64

My RV64 CPU (Work in progress)

documentation_spike

Documentation for RISC-V Spike

gap

A generic agent pattern that can be reused with multiple interfaces/protocols

gp-thesis

Latex files for graduation project thesis

gpcore

This is the base repo for our graduation project in AlexU 21

hdl

This repository contains scripts that I create through my digital design course in Verilog, VHDL, SystemVerilog etc..

hls

misc-python

A repository for miscellaneous python mini projects

ohtl-performance

Overhead transmission line performance (voltage and current at sending end, the voltage regulation, and efficiency) calculator knowing the line parameters, receiving end power, voltage, power factor and the length of the transmission line.

pong4two

C++ND Capstone Project

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

ri5cy

riscv-software-list

The RISC-V software tools list, as seen on riscv.org

rivet

rtlblocks

Common RTL blocks I use

sc-mips

Single-cycle single-core MIPS processor

scripts

Basic scripts that I use

sparcemem

tev

RV32/64IMAC Core

uvm-rv

vbalance

vlsi-notes

Digital IC design and vlsi notes