Possible to get the Core Generator project for the ZTEX source project? about john HOT 9 OPEN

There are a few low cost FPGA's available, where it also fits, not so many cores though, which is the one's I'm trying to implement the code for, I'll let you know ow it goes.

from john.

Hi @Apingis! Long time no talk. Are you around and available to comment on this request, please? Thank you!

from john.

from john.

I've figured that the rd_clk and wr_clk must be the FIFO clocks, I try figure out the rest

from john.

That's great @plj567. It doesn't look like we're going to hear from @Apingis here, so maybe once you figure things out you'd add a documentation file on your findings, to help others possibly get into this as well?

What other FPGA boards are you porting to? What do you intend to do with the host and communications and firmware code, which is now specific to ZTEX's usage of USB? Is your port intended to be part of JtR at all, or a separate project? Thank you!

from john.

I'm trying to get it to work on two other boards at the moment, not sure if it's worth the effort which is why I'm investigating some other sha256 & sha512 sources, if I complete it I will update and provide the board information as well

from john.

Out of the algorithms we support on FPGA, it's bcrypt and descrypt where FPGAs are most competitive vs. GPUs. We also have some algorithms based on SHA-2 to allow such reuse of the hardware as well, but we assume the reason someone would acquire FPGAs is for bcrypt and descrypt. Your focus on SHA-2 suggests your use case is different. You'd have to have larger FPGAs at low cost for doing solely SHA-2 on them to be worthwhile, and that feels unlikely.

from john.

Hi plj567, what are the FPGA boards for which you want to implement the code?

from john.

Hi @plj567! Any update on your project?

from john.