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Muhammad Shameel Ansari photo

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followers: 0.0 following: 3.0 repos: 11.0 gists: 0.0

Name: Muhammad Shameel Ansari

Type: User

Company: Micro Electronics Research Laboratory - MERL

Bio: Research Associate @MERL-DSU | VLSI | SystemVerilog | UVM | PY-UVM | ASIC Verification Engineer | Data Science | Visiting Faculty @DSU | Python | FPGA | RISC-V

Location: Karachi, Sindh Pakistan

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Hi šŸ‘‹, I'm Engr. Muhammad Shameel Ansari

A Passionate ASIC Design & Verification Engineer from Pakistan. I am an Electrical Engineer and ASIC professional specializing in ASIC RTL Design, Verification, and FPGA Emulation. Proficient in languages such as C++, Verilog, SystemVerilog, UVM, PYUVM, and Python, I bring a robust background in semiconductor research, having designed IPs and conducted UVM-based verifications. I've also contributed to the MPW6 competition, showcasing my commitment to innovation. As a visiting faculty at DHA Suffa University, I enjoy sharing my expertise in Microprocessor design! šŸš€šŸ’”

Coding

muhammadshameelansari1999

  • šŸ”­ Iā€™m currently working on Designing PWM IP Peripheral

  • šŸŒ± Iā€™m currently learning SystemVerilog, UVM

Connect with me:

mshameelansari19 @muhammadshameelansari1380 @merldsu

Languages and Tools:

arduino c cplusplus linux matlab python qt Redux Redux Redux Redux Redux

muhammadshameelansari1999

Ā muhammadshameelansari1999

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Muhammad Shameel Ansari's Projects

rtl_design icon rtl_design

This Repo contain Basic RTL Design Examples Code in SystemVerilog.

sap_fpu icon sap_fpu

This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.

sap_fpu_verification icon sap_fpu_verification

This repository contains the Graphical User Interface (GUI) of the Verification Environment of SAP-FPU.

uvm_env icon uvm_env

This Repo contain UVM Verification Examples.

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