A Passionate ASIC Design & Verification Engineer from Pakistan. I am an Electrical Engineer and ASIC professional specializing in ASIC RTL Design, Verification, and FPGA Emulation. Proficient in languages such as C++, Verilog, SystemVerilog, UVM, PYUVM, and Python, I bring a robust background in semiconductor research, having designed IPs and conducted UVM-based verifications. I've also contributed to the MPW6 competition, showcasing my commitment to innovation. As a visiting faculty at DHA Suffa University, I enjoy sharing my expertise in Microprocessor design! šš”
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š Iām currently working on Designing PWM IP Peripheral
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š± Iām currently learning SystemVerilog, UVM