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awesome-dv

Awesome ASIC design verification

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi-ethernet-uvm

A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM

axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

chinese-translation-of-pci-express-technology-

Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare

corundum

Open source FPGA-based NIC and platform for in-network compute

cosmos-openssd

cosmos-plus-openssd

Cosmos OpenSSD + Hardware and Software source distribution

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

ethernet-fmc-axi-eth

Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks

ethernet_10ge_mac_sv_uvm_tb

SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core

hbird-sdk

OpenSource HummingBird RISC-V Software Development Kit

hit-oslab

S - 哈工大《操作系统》实验

isp_uvm

A Framework for Design and Verification of Image Processing Applications using UVM

kkndme_tianya

天涯 kkndme 神贴聊房价

learngit

linux-xlnx

The official Linux kernel from Xilinx

ml-for-beginners

12 weeks, 24 lessons, classic Machine Learning for all

practical-uvm-ieee-edition

This is the repository for the IEEE version of the book

pynq_softmax

achieve softmax in PYNQ with heterogeneous computing.

riffa

The RIFFA development repository

rkic_virtualmachine_update

sdram-verification

This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed by Dinesh in Opencores.org

ucore

清华大学操作系统课程实验 (OS Kernel Labs)

verilog-ethernet

Verilog Ethernet components for FPGA implementation

yuu_ahb

UVM AHB VIP