Add self-modifying code stress test trace about mips-traces HOT 9 CLOSED

I would like to have a real stress test with many cases of self-modifying code (SMC). It should be in a single file (smc.s). The trace begins with the simplest case: modifying instruction is executed ~10 instruction before instruction it modifies, than the gap becomes closer: 4, 3, 2, 1, 0 instructions.

What instructions should we not use for filling?

• Branches
• Loads
• Multiplication/Division

so we use only simplest logical instructions and stores to create SMC context.

Each modified instruction must be followed by a checking instruction which compares its result with the expected result. If the actual result does not match expected result, execution jumps to error output (please, copy it exactly from tt.core.s).

Please check at least 3 types of modification of ALU instructions:

• Modification of immediate (addi %r1, %r2, $5 -> addi %r1, %r2, $a5)
• Modification of register (addi %r1, %r2, $5 -> addi %r3, %r1, $5)
• Modification of opcode (add %r1, %r2, %r2 -> sub %r1, %r2, %r2)

Then you check SMC on branches. I suggest to use one case but test it with different gaps (10, 4, 3, 2, 1, 0):

• j $old_target → j $new_target

It would be nice to add the new trace to our test suites, but I'll create separate issue for this.

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@qsuo I would like to use this trace for demonstration on lecture on 10 Nov. It would be nice if you complete the task before that deadline.

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@qsuo Danil, do you have any progress with that?

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@pavelkryukov yes, I'm in process

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Ok, nice to hear. Please let me know if there is a problem.

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Example of SMC: https://github.com/rweics/Curry-fun

To load absolute address of a label, use la pseudoinstruction

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By the way, the author uses a nice trick: he loads an instruction from some unreachable code and than stores it.

smc:
  add $t0, $t1, $t2
  la $t0, new_instr
  lw $t0, 0x0($t0)
  la $t1, smc
  sw $t0, 0x0($t1)
  jr $ra ; something to never reach code below
new_instr:
  and $t0, $t1, $t2

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@pavelkryukov I don't understand task completely. We should insert ~10 instructions between intruction, which we want to modificate, and the instruction which modificate, shouldn't we? Somthing like this

    la $t1, new
    lw $t0, 0($t1)
    la $t1, smc

    sw $t0, 0($t1)

    #~10 insrtuctions
 
smc:
    
    add $t0, $t1, $t2 

new:
    and $t0, $t1, $t2

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Yes, you understood it correctly.

Let me give some motivation. On previous lecture we studied a "single-cycle" implementation of CPU, it executes next instruction if and only if the previous one is completed. That approach is very naïve. Real high-end CPUs overlap execution of different instructions through pipelines, so the old version of instruction may be executed if there is no special handling introduced. If there is a 10 instructions gap, MIPT-MIPS CPU won't be affected, but decreasing the gap will introduce some problems.

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