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axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

books---a-primer-on-memory-consistency-and-cache-coherence

A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划

bsv-domain-specific-hardware-accelerator-vlsi-cad-project

Domain Specific Hardware Accelerators - VLSI CAD Project

cpp_etudes_calltree

smart tools for source code study : cpptree.pl, calltree.pl, javatree.pl, java_calltree.pl

emacs-resources

emacs config, with out use package install for some mechine not has internet for package install

hello-algo

《Hello 算法》：动画图解、一键运行的数据结构与算法教程，支持 Python, C++, Java, C#, Go, Swift, JS, TS, Dart, Rust, C, Zig 等语言。English edition ongoing

rtl-design-hdl-reference

HDL libraries and projects

rtl-design-riscv-bsv-refer-flute

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

rtl-design-riscv-e203_hbirdv2

The Ultra-Low Power RISC-V Core

rtl-designs-riscv-bsv-refer-piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

rtl-language-bsv-bsv_tutorial_cn

爆肝6万字的 Bluespec SystemVerilog (BSV) 中文教程

rtl-lib-common_cells

Common SystemVerilog components

rtl-tools-emacs-verilog-mode

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

rtl-tools-language-bsc

Bluespec Compiler (BSC)

rtl-tools-perl-hdlgen

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

rtl-tools-vim-automatic-verilog

automatic-verilog based on vimscript

rtl-tools-vim-verilog_systemverilog.vim

Verilog/SystemVerilog Syntax and Omni-completion

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

verilog-ext

Verilog Extensions for Emacs

vim-resources