Comments (3)
MajicDesigns
commented on June 10, 2024
1
Checking in the data sheet, data is latched in to the MAX72xx hardware on the rising edge of the CS pin, so what is described is a possible scenario. Eliminating the line as proposed or setting the I/O to LOW are the solution. Code will be changed and published in the next release (low priority).
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MajicDesigns
commented on June 10, 2024
Never seen this happen, but it is possible. What hardware are you using and are you implementing the slower software SPI interface?
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elan
commented on June 10, 2024
Custom hardware, with hardware SPI.
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