dmpro16's Introduction

Project for dmpro 2016

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Documents structure

Location	Description
`documents/deliveries`	contains a directory per delivery. Everything that is to be delivered is placed here and is compiled into a pdf/LaTeX before delivery
`documents/documentation`	contains all design documents, facts and data about our system and the components used in it.
`documents/documentation/datasheets/`	contains datasheets for components used.
`documents/meetings`	contains meeting minutes from all meetings, sorted by date
`documents/research`	contains research notes on components, algorithms, circuits, application notes and datasheets for potential components etc.
`documents/todo`	task lists, with deadline

mcu: code running on the EFM32
fpga: code running on the FPGA
- Folder for each module
prototyping: code not running in final product
- Folder for each prototype program

dmpro16's People

It looks like Xilinx removed the SUSPEND mode from 7-series FPGAs, so there is no explicit sleep mode to be triggered.

Clock gating (stopping the clock while not in operation) is still an option and is discussed in page 57 of the following:
http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

So the clock is passed through a BUFGCE (clock buffer) with an enable signal to enable or disable that entire region. Here's a small Verilog example on this:
https://forums.xilinx.com/t5/Timing-Analysis/FPGA-clock-gating-implementation/td-p/548555

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