Comments (5)
hriener
commented on August 24, 2024
I pushed a branch bugfix_2019_07.
Does that resolve the issue for you?
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fabrizioferrandi
commented on August 24, 2024
Yes, thank you very much for the quick fix.
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hriener
commented on August 24, 2024
Fixed in PR #179.
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fabrizioferrandi
commented on August 24, 2024
Not sure anymore sure that the issue has been fixed. I've checked what collapse_mapped_network<klut_network>( mapped_aig ) returns.
The current code returns this bench:
INPUT(n2)
OUTPUT(po0)
n0 = gnd
n1 = vdd
n3 = LUT 0x2 (n2)
po0 = LUT 0x2 (n3)
which is wrong.
n3 = LUT 0x1(n2)
is the correct answer. In other words, the initial bench describes the boolean expression a ^ 1 which is equivalent to !a. The collapse seems to return a. Am I missing something?
Fabrizio
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msoeken
commented on August 24, 2024
We are working on a work-around through cleanup_luts with constant propagation.
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Related Issues (20)
- Bug in refactoring HOT 3
- Write a sequential circuit with register outputs.
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- Bug in aqfp_flow_date HOT 1
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- `write_blif` incorrect behavior when PO is connected to PI of the same index HOT 4
- `aig_resubstitution` following `cut_rewriting` without `cleanup_dangling` in between creates NEQ circuits HOT 3
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- How to reproduce DATE20 Exact DAG-Aware Rewriting? HOT 1
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