Comments (5)
I pushed a branch bugfix_2019_07
.
Does that resolve the issue for you?
from mockturtle.
Yes, thank you very much for the quick fix.
from mockturtle.
Fixed in PR #179.
from mockturtle.
Not sure anymore sure that the issue has been fixed. I've checked what collapse_mapped_network<klut_network>( mapped_aig ) returns.
The current code returns this bench:
INPUT(n2)
OUTPUT(po0)
n0 = gnd
n1 = vdd
n3 = LUT 0x2 (n2)
po0 = LUT 0x2 (n3)
which is wrong.
n3 = LUT 0x1(n2)
is the correct answer. In other words, the initial bench describes the boolean expression a ^ 1 which is equivalent to !a. The collapse seems to return a. Am I missing something?
Fabrizio
from mockturtle.
We are working on a work-around through cleanup_luts
with constant propagation.
from mockturtle.
Related Issues (20)
- Bug in refactoring HOT 3
- Write a sequential circuit with register outputs.
- `write_blif` outputs duplicate `.names` HOT 4
- Optimization algorithms to support names_view<sequential<xxx_network>> HOT 1
- lut_map creates non-equivalent network HOT 1
- Bug in aqfp_flow_date HOT 1
- NEQ bug in new LUT mapper HOT 1
- Technology Mapping of sequential aig fails. HOT 2
- `write_blif` incorrect behavior when PO is connected to PI of the same index HOT 4
- `aig_resubstitution` following `cut_rewriting` without `cleanup_dangling` in between creates NEQ circuits HOT 3
- `refactoring` using `sop_factoring` assertion fails in `mffc_view` HOT 2
- How to reproduce DATE20 Exact DAG-Aware Rewriting? HOT 1
- Thank you, there is a problem, could you please help me. HOT 2
- Non-deterministic behavior in ESOP computation HOT 1
- What if I want to use original ABC with mocktutle? HOT 3
- The `blif_reader` to mig directly is not worked as expected HOT 3
- Convert a behavioural level verilog file to MIG network
- Convert behavioral level Verilog file to MIG network HOT 2
- Getting parse errors when reading Verilog files using Lorina Verilog reader HOT 5
- Writer/Reader combination that supports `names_view` HOT 1
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