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Comments (5)

sjgitty avatar sjgitty commented on July 22, 2024

Feels like we're doing this already. Alex, what is the status of this issue?

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sjgitty avatar sjgitty commented on July 22, 2024

Marking 'move to IP' but @asb is this still un-done?

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aytong avatar aytong commented on July 22, 2024

@asb what's the current status of this task? If it is still open, suggest downgrade to P3. WDYT?

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asb avatar asb commented on July 22, 2024

There's been no movement on it and I think it's probably still a P2. If anything we should look at upgrading the priority post launch.

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kal-ne avatar kal-ne commented on July 22, 2024

Hi I'm new to open source. I would like to try and understand this issue and see if I can help. I'm currently reading OpenTitan Docs and setting up the Environment.

I just wrapped up a 6 month internship in EDA domain where I worked in functional verification and was exposed to Verilog, SystemVerilog and UVM. Worked on testing related to AXI 4 and i2c.
I have some exposure to C++(from 2015), worked(first time) with python scripts and ROS last year.

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