Comments (1)
@imphil
my understanding is that this is already done. Can we close this now?
from opentitan.
Related Issues (20)
- [chip-test, clkmgr] chip_sw_clkmgr_escalation_reset
- [chip-test, keymgr] chip_sw_keymgr_key_derivation
- [chip-test, keymgr] chip_sw_keymgr_sideload_kmac
- [chip-test, keymgr] chip_sw_keymgr_sideload_aes
- [chip-test, keymgr] chip_sw_keymgr_sideload_otbn
- [chip-test, keymgr] chip_sw_keymgr_derive_attestation HOT 1
- [chip-test, keymgr] chip_sw_keymgr_derive_sealing
- [chip-test, spi_device] chip_sw_spi_device_pass_through
- [chip-test, spi_device] chip_sw_spi_device_pass_through_flash_model HOT 1
- [chip-test, spi_device] chip_sw_spi_device_pass_through_collision
- [chip-test, spi_device] chip_sw_spi_device_tpm
- [chip-test, spi_device] chip_sw_spi_device_output_when_disabled_or_sleeping HOT 1
- [chip-test, aes] chip_sw_aes_masking_off
- [rv_dm,dv] Smoke vseq is broken for some seeds HOT 2
- [dvsim] Questa uart_smoke failing at tl_agent_pkg load HOT 5
- [GPIO] Interrupt description is not accurate HOT 1
- [dv,cov_merge] Merge serially with vcs, not in parallel
- [fpga, docs] Guidance on migrating design to a new FPGA
- [dv,csr] Stop transaction generation for random resets HOT 3
- [spi_device] Optimize CS pin on at most 1-2 pinmux paths HOT 6
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