Related Issues (20)
- [questa] known-good output from passing sims
- [test-triage] i2c_target_hrst HOT 1
- [cryptolib] Allow garbage collection when linking OTBN binaries to reduce code size HOT 11
- [ot_certs,opentitantool] enable generating certificates in CBOR format HOT 3
- [hmac,dv] Break up NIST test vector HOT 1
- [spi_host] Missing TXEMPTY interrupt on Z1 silicon HOT 3
- [dvsim] Automatically generating reproduction commands in regression logs
- [test-triage] flash_ctrl - Check failed on interface flash_ctrl_eflash_reg_block
- [usbdev] vcs simulation error HOT 2
- [rom_ctrl,dv] Fix invalid check in scoreboard
- [rom_ctrl,dv] The stress_all_with_rand_reset sequence mostly fails
- [rom_ctrl,dv] Tweak the mask for invalid digests in rom_ctrl_base_vseq
- [rom_ctrl,dv] Make some assertions terminate
- [tmp]
- [AES, doc] Missing De-initialisation section in https://opentitan.org/book/hw/ip/aes/doc/theory_of_operation.html
- [manuf] finalize device ID format for Earlgrey PROD
- [dv,dvsim,tooling] Questa Support HOT 2
- [gap analysis] Synopsys VC Formal (unreachability) support
- [test-triage] `otbn_sec_cm` failures
- [test-triage] chip_sw_pwrmgr_random_sleep_all_reset_reqs assertion `noOutstandingReqsAtEndOfSim_A` fails in `tlul_assert.sv`
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