Speed test fails at DIV=0, reverts to lower speed about litespi HOT 1 CLOSED

I debugged this last night and found several issues preventing this from working at DIV=0:

• pads.clk is normally registered with a SDROutput, but not when being output through the USRMCLK primitive, resulting in it being output too early. At DIV=0 this shifts it 180° out of phase, resulting in the flash not interpreting the command correctly.
• The clock generator is glitching at the IDLE state between the DUMMY and DATA states, which at DIV=0 results in an extra clock pulse being output.
• Since both the output and the input is registered with a SDRTristate, the input data arrives two cycles after the output data is written. At DIV=0 this means that the previous input arrives in the same cycle as the next output, which means that the last input bit doesn't arrive before we've left the DATA state.

I've fixed the first two issues and worked around the third, so I have something that works now, but it requires a bit more work before it's ready to be submitted as a PR.

from litespi.