Comments (3)
Dolu1990
commented on August 17, 2024
Long answer there : SpinalHDL/VexRiscv#85 (comment)
But to resume :
- Coherent D$
- Coherent interconnect
- But first i would like to boost the I$ D$ memory bus data width first. Would that be fine in litex ?
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enjoy-digital
commented on August 17, 2024
@Dolu1990: thanks. Yes increasing the memory bus data width will be possible (and we'll probably work on that soon since this is also useful for Rocket that is currently down-converted to 32-bit (just to have a first working version) but should be 64-bit).
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enjoy-digital
commented on August 17, 2024
#47 and #126 are duplicate, let's continue the discussion in #126.
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