larsasplund Goto Github PK
Name: Lars Asplund
Type: User
Lars Asplund's Projects
a2i
compliance-tests
corelib
A VHDL Core Library.
gha_tests
Playing around with GHA
github-facts
GitHub-based statistics highlighting interesting facts about the HDL industry
json-for-vhdl
A JSON library implemented in VHDL.
matlab_integration
Example of VUnit Matlab integration
microwatt
A tiny Open POWER ISA softcore written in VHDL 2008
neorv32
A size-optimized, customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
open-source-fpga-resource
A list of resources related to the open-source FPGA projects
osvvm
Open Source VHDL Verification Methodology (OSVVM) Repository
playground
Develop the directors structure and testing infrastructure for CoreLib
sigasi_insights
splitting_signals
synchronization
Synchronization mechanisms for VHDL
tb_drain_strategy
udp_ip_stack
UDP IP stack example project from this VUnit getting started blog (https://www.linkedin.com/pulse/vunit-best-value-initial-effort-lars-asplund)
vhdl2008-tester
Scripts to test which features from VHDL 2008 are supported by your compiler.
vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
vunit_attributes
Demonstrate VUnit attributes
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