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-effective-python-

<파이썬 코딩의 기술> Effective Python 이펙티브 파이썬

3d-resnets-pytorch

3D ResNets for Action Recognition (CVPR 2018)

advanced-embedded-system-design-flow-on-zynq

aspolos2019-packing-column-combine

bismo

BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing

bnn-fpga

Binarized Convolutional Neural Networks on Software-Programmable FPGAs

convnet.pytorch

ConvNet training using pytorch

convolutional-neural-network

Implementation of CNN using Verilog

cs294-112-homework

Assignments for CS294-112.

deep-compression-pytorch-pruning

PyTorch implementation of 'Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding' by Song Han, Huizi Mao, William J. Dally

deep-learning-with-keras

Code repository for Deep Learning with Keras published by Packt

designcnnaccelerators

Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017

diracdeltanet

PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

dl_cv_tensorflow_10weeks

딥러닝-영상인식 CAMP 10주 과정을 위한 TensorFlow 코드들

dl_with_pytorch

dnnweaver2

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

dotfiles

💻⚒️⚒️ Curated Linux dotfiles selection

dramsim2

DRAMSim2: A cycle accurate DRAM simulator

dscodereview

ece5775

Code repo for labs of ECE 5775 High-Level Digital Design Automation Fall 2018 at Cornell

eecv2018-amc-training

[ECCV 2018] AMC: AutoML for Model Compression and Acceleration on Mobile Devices.

enas-tf-macro

TensorFlow Code for paper "Efficient Neural Architecture Search via Parameter Sharing"

espnetv2

A light-weight, power efficient, and general purpose convolutional neural network

first-steps-with-tensorflow

도서 '텐서플로 첫걸음'의 예제 주피터 노트북입니다.

fpga-design-flow-using-vivado

This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite

gct634-2019

GCT634 Musical Applications of Machine Learning Homework

gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

haq

[CVPR 2019, Oral] HAQ: Hardware-Aware Automated Quantization with Mixed Precision.

hardware-lab

heterocl

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing