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amba

Collection of IPs based on AMBA (AHB, APB, AXI) protocols

arty_xjtag

Xilinx JTAG Toolchain on Digilent Arty board

awesome-selfhosted

A list of Free Software network services and web applications which can be hosted on your own servers

axi_node

AXI X-Bar

biriscv

32-bit Superscalar RISC-V CPU

bsp-xilinx

cmd_vivado

Simplified Command Line Interface to Xilinx's Vivado IDE

cocotb-example

code_helper

core_usb_bridge

USB -> AXI Debug Bridge

cores

Various HDL (Verilog) IP Cores

cores-swerv-el2

SweRV EL2 Core

cores-swervolf

FuseSoC-based SoC for SweRV EH1

crawler_rent_591

daisho

Test of the USB3 IP Core from Daisho on a Xilinx device

darkriscv

opensouce RISC-V implemented from scratch in one night!

dearpygui

Dear PyGui: A fast and powerful Graphical User Interface Toolkit for Python with minimal dependencies

fpga-ftdi245fifo

FPGA-based USB fast communication using FT232H/FT600 chip.

fpga-spi

Simple SPI interface for FPGAs

gen_amba

AMBA bus generator including AXI, AHB, and APB

hwt

VHDL/Verilog/SystemC code generator, simulator writen in python/c++

imgui

Dear ImGui: Bloat-free Graphical User interface for C++ with minimal dependencies

litex

Build your hardware, easily!

mriscvcore

A 32-bit RISC-V processor for mriscv project

mymdwiki

Mdwiki

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

nicegui

High-Level Abstraction Web-GUI Using Just Python.

notence

📝 An open source personal note-taking app inspired by notion.so (Alpha📌)

pars

pointer_queue

C99 queue base on pointer buffer