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a-convolution-kernel-implemented-by-vivado-hls

This project implements a convolution kernel based on vivado HLS on zcu104

accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

artix_7

My experiments with Nexys4 DDR Artix-7 FPGA Board

cnn-facial-landmark

Training code for facial landmark detection based on deep convolutional neural network.

cnn-using-hls

Convolutional Neural Network Using High Level Synthesis

control-systems

A bundle of necessary functions in the domain of control systems

designlab

digital-design-of-fir-filter

Hardware Design and Verification of a configurable and parametrized 50th order low-pass FIR filter starting from MATLAB Modeling to Verilog RTL Design and Simulink Testing with .wav audio files.

driver_drowsiness_system_cnn

This is a system which can detect the drowsiness of the driver using CNN - Python, OpenCV

embedded-systems-mini-projects

face_detection_hls

with maxi port

fifos

Register-based and RAM-based FIFOs designed in Verilog/System Verilog.

floatingpointmac_with_fifo_on_fpga

This digital design project was created for the course EE271 in SJSU.

fpga_pio

An attempt to recreate the RP2040 PIO in an FPGA

hacktoberfest17

Make PRs and win Tee and stickers

hacktoberfest18

helloworld

my first github

hls-cnn

High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.

introduction-to-soc-design-education-kit

Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals

lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

matmul-2020.2

A floating-point matrix multiplication implemented in hardware

mips32_pipelinecpu

A MIPS32 CPU project with five-stage pipeline.(EI332 Course Project 3)

nandland

All code found on nandland is here. underconstruction.gif

pipeline-cpu-mips32

基于MIPS32指令集（部分指令）的五级流水线CPU。验证方法：使用指令跑通了斐波那契数列（可用寄存器指定项数）。

pipelined-fpmac-system

Course Project implemented on Nexus A7 FPGA

poc

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

programming_practice

project_code

pynq_tutorials

qiskit-textbook

A university quantum algorithms/computation course supplement based on Qiskit