Joyen Benitto's Projects
Antenna_generator is a tool developed with researchers in the field of antenna design in mind. In a nutshell antenna_generator is a python package that allows you to generate microstrip patch antenna in the HFSS software, we have added support for optimizations like cut-out, slots and L slot.
Learning bluespec with bunch of tutorials and example codes
CUDA-101 Workshop
Understanding data level parallelism with CUDA
FleetVision - HashCode 11 Hackathon Project
Giggle is a tiny static site generator
Learning go
grape is a single cycle RISC-V [RV32I] processor synthesised using SystemVerilog. This project was done as a part of the RISC-V Architecture course(UE20EC302). This my first attempt in building a processor.
Learning LLVM by building a compiler
In this repository we begin our journey with simulating basic C code for a RISC-V processor.
In this repo I explore opensource EDA tools and PD of ASIC design flow.
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
RISC-V Configuration Validator
Spike, a RISC-V ISA Simulator