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cxl_type3_tests

This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Devices

cxlmemsim

A place to store the CXL simulator

dramsim2

DRAMSim2: A cycle accurate DRAM simulator

gem5-cxl

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

hdl_converter

A simple tool that can be used to convert the header syntax of a verilog module or VHDL entity to an instantiation syntax and create testbench structures (top level and verify). The project is aimed at removing the need for tedious refactoring of module headers when instantiating modules or verifying individual modules with testbenches.

hello

react-tetris

Use React, Redux, Immutable to code Tetris. 🎮

smdk

SMDK, Scalable Memory Development Kit, is developed for Samsung CXL(Compute Express Link) Memory Expander to enable full-stack Software-Defined Memory system