Comments (2)
This is a remnant from the fact that this code was originally based on my CPU Raytracer project.
The idea there was that since each BVHNode2 is 32 bytes, you can exactly fit the 2 children of a node inside a single 64 byte cacheline. This cacheline would then (hopefully) need to be loaded only once from RAM during BVH traversal, thereby improving performance.
Note that this is assumes that the BVH nodes array itself is aligned to 64 bytes (which I did ensure in the CPU tracer), but I didn't actually ensure in this project. So the benefit is sort of lost here.
I guess the reason I didnt bother here is that I expect less of a performance improvement since I dont actually traverse the BVH on the CPU side. On the other hand maybe the BVHOptimizer could benefit from the cache locality, so perhaps I should try out using an aligned allocation for the BVH nodes here as well.
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I got it. Thank you very much.
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Related Issues (15)
- Stuck in operation HOT 2
- How to actually build this? HOT 5
- Problems with SBVH construction HOT 1
- Impressive ! (issue about license) HOT 1
- An error occurred during Reset buffer sizes HOT 4
- qbvh and other bvhs HOT 6
- General questions HOT 25
- Building on CUDA 10.2. Problem with CUDA_ERROR_LAUNCH_OUT_OF_RESOURCES. HOT 7
- [Question] Samples HOT 2
- instances in CWBWH HOT 2
- imask and meta field in BVH8 converter HOT 1
- ray_cone_angle typo in sort kernel HOT 1
- Does it render in real-time? HOT 2
- Will the latest CUDA 12.01 work? HOT 5
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