Comments (4)
For those who are still interested, this paper is a good read, A Quantitative Analysis and Guideline of Data Streaming Accelerator in Intel® 4th Gen Xeon® Scalable Processors
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Hello,
What document are you referring to? Is it DML documentation or DSA specification?
DML is a software layer that enables DSA, that is correct.
We've added Library Architecture Overview for the similar library, called QPL (for IAA support), I wonder if this could be helpful to get a better overall understanding.
Just to clarify, hardware_path
(Low-Level API) or dml:hardware
(High-Level API) is for offloading operation fully to accelerator. There could be portion of work done on the host, but in most of the cases it is just some preparatory work before offloading. Asynchronous execution on hardware_path
is basically about submitting a job and periodically checking whether it is completed (with submit and check done on users side), synchronous interface does the same, but on library side (as if under single API we call submit and periodically check completion).
software_path
/ dml::software
is for executing the operation on the host only. So for this path, there is no asynchronous API (submit).
automatic_path
/ dml::auto
currently is very straightforward and submits job to DSA first, and in the case of error, do re-try (or continue) on the host. This could be potentially extended to include heuristics for choosing whether to execute on host or accelerator, or extended to divide work between those.
Hope this helps!
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Thank you for your quick response!
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@mzhukova I apologize for reopening this issue, but I still have some related follow-up questions that I would like to ask you.
DSA is a target for offloading many functions. However, before DSA, there was also on-chip DMA in I/OAT similar to DSA. I understand that DSA has more features than DMA, but if we only consider memory copy, is DSA faster than DMA? Additionally, will DML support DMA "hardware"?
Thank you once again!
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Related Issues (20)
- examples not getting compiled by default HOT 2
- Excessive initialization in descriptor and completion_record HOT 4
- DSA cache control bit is not flush operation specific HOT 2
- HW path does not work with job_api_example HOT 5
- segfault with mutli-thread since the port ptr become null HOT 3
- include/dml/detail/ml/buffer.hpp uses std::exchange but does not #include <utility> HOT 5
- Debugging hardware path on Sapphire Rapids HOT 6
- Possible use-after-free when handler is destroyed before operation completes? HOT 2
- Incorrect handling of PAGE_FAULT_MASK HOT 3
- Incorrect handling of CRC HOT 2
- Incorrect patterns in update_**_for_continuation HOT 1
- compiler optimization issue when allocation the transfer buffer on heap memory HOT 3
- An issue about Multi-Socket sample code HOT 4
- Question about async mode of DML HOT 3
- "404 page not found" for issue reporting link HOT 2
- Unknown buffer size limitation for CRC operation HOT 8
- A question about dml_finalize_job HOT 3
- Fails to build from source (FTBFS) on Windows
- Error when using hardware path HOT 7
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