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iamrk-vlsi

Config files for my GitHub profile.

open-source-rtl-design

This repository contains overview of things carried out during VSD "RTL Design Using Verilog With SKY130 Technology" workshop

risc-v-myth-workshop

5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !

risc-v-myth-workshop-august-designerguy13-photonics

risc-v-myth-workshop-august-designerguy13-photonics created by GitHub Classroom

risc-v-myth-workshop-august-harinarayan18

risc-v-myth-workshop-august-harinarayan18 created by GitHub Classroom

risc-v-myth-workshop-august-iamrk-vlsi

risc-v-myth-workshop-august-iamrk-vlsi created by GitHub Classroom

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

rtl_design_and_synthesis_using_sky130pdk_yosys_iverilog

This github repo is to document the 5day "RTL Design and Synthesis using Verilog and Sky130 library" which was conducted by VLSI System Design Corp.

rtl_design_with_sky130

rtldesignusingverilogwithsky130technology

sky130-rtl-design-workshop

VSD Workshop on RTL Design using Verilog HDL and Synthesis with Optimization using SKY130 Technology

sky130-vlsi-workshop

VSD-IAT repository for workshop

sky130rtldesignandsynthesisworkshop

tcam

TCAM ( Ternary Content-Addressable Memory) on Verilog