.github

hvhdl

documentation pages for High Level Synthesizable VHDL (hVHDL) libraries

hvhdl_analog_to_digital_drivers

Analog to digital drivers for Sigma Delta Modulators with high level interfaces

hvhdl_dynamic_model_verification_library

Synthesizable VHDL models for HiL Simulation

hvhdl_example_project

An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs

hvhdl_fixed_point

VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.

hvhdl_floating_point

high level VHDL floating point library for synthesis in fpga

hvhdl_fpga_interconnect

interconnecting bus written in VHDL for accessing data in FPGA modules

hvhdl_gigabit_ethernet

VHDL library for synthesizable minimal gigabit ethernet with RGMII interface, minimal ethernet, ip and udp header parsers.

hvhdl_memory_library

Memory library written in VHDL for synthesis

hvhdl_microprogam_processor

VHDL module for running operations from memory with the software also written in vhdl

hvhdl_uart

VHDL library for uart with abstracted interface for easy application.