Comments (2)
You might find the following resources interesting;
Google has continued to work heavily with Antmicro to push forward the state of open source memory controller solutions. Our current focus has been around making sure we are able to explore current issues around RowHammer. See the following links;
- https://opensource.googleblog.com/2021/11/Open%20source%20DDR%20controller%20framework%20for%20mitigating%20Rowhammer.html
- https://cfp.openpower.foundation/summit2021/talk/C9Q3GS/
- https://antmicro.com/blog/2021/04/lpddr4-test-platform/
- https://security.googleblog.com/2021/05/introducing-half-double-new-hammering.html
- https://github.com/antmicro/litex-rowhammer-tester
- https://litex-rowhammer-tester.readthedocs.io/en/latest/
- https://github.com/antmicro/lpddr4-testbed
- https://github.com/antmicro/lpddr4-test-board
- https://github.com/antmicro/data-center-dram-tester
- https://github.com/enjoy-digital/litedram
While the memory controller is being actively developed on FPGAs, we have also started work on making sure that it can also be used in ASIC solutions. The current plan is to do tape outs of this controller in both SKY130 and GF12LP technologies in 2022 using only open source tooling like OpenROAD for the digital blocks. This means we will also need open source PHYs to make this possible and are actively working to build out that area too.
Also take a look at https://github.com/waviousllc/wav-lpddr-hw
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There are also multiple examples of integrating LiteDRAM into non-Migen designs (like MicroWatt).
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Related Issues (16)
- Consider doing a tapeout using SKY130 using Google's no cost shuttle program HOT 2
- FV on the Current Design HOT 3
- CMake issues HOT 5
- Generation of files in "examples/direct/expected" HOT 2
- Open gpu v HOT 1
- DOes this contain hardware ? HOT 1
- Code coverage report HOT 2
- [doc] Awesome! How to get started? - Quick Start Readme HOT 3
- deviations from RISC-V HOT 6
- PCIe 4+ interface HOT 1
- Network on a Chip (NoC) implementation HOT 1
- Does anyone have an understanding into the trade-offs of providing an instruction pointer to each core, or only to each computer unit?
- Why not fully RISC-V compliant?
- Implement into VAAMAN!
- Any specific environment? HOT 2
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