About the counter-intuitive herd7 simulation result for CoRW1+fence.rw.rwspx.litmus about herdtools7 HOT 2 CLOSED

Hi @DehengYang. I do not know about specific behaviour guarantee for this RISCV.

However, generally speaking, store conditional may fail for just any reason. Here is a naive scenario:

The running thread is scheduled out just after the load-reserve instruction has been executed. In such a case, the reservation is likely to be cancelled.

The scenario is naive. If (1) the store conditional instruction immediately follows the load reserve instruction and (2) that the reserved memory it is certain not to be accessed that any other thread, then it may be the case that the store conditional will always succeed. Yet, I doubt that official documentation would say that. Moreover, would it be the case, I am not sure we would implement such a particular case.

Hope it helps.

from herdtools7.

Hi @maranget ,

Thank you so much for the detailed explanation and analysis that perfectly solves my confusion.

Many thanks and wish you a great week!

Yours sincerely,
Deheng

from herdtools7.