haplv Goto Github PK
Name: Hap
Type: User
Hap's Projects
computer-science-textbooks
Collect some CS textbooks for learning.
dramsim3
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
e203_hbirdv2
The Ultra-Low Power RISC-V Core
easyspider
A visual no-code/code-free web crawler/spider易采集：一个可视化浏览器自动化测试/数据采集/爬虫软件，可以无代码图形化的设计和执行爬虫任务。别名：ServiceWrapper面向Web应用的智能化服务封装系统。
gem5
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
hdlgen
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
integrated-circuit-textbooks
Collect some IC textbooks for learning.
learning_research
本人的科研经验
linux101-docs
Linux 101 学生课程教材与讲义
misato
RISC-V Processor written in Amaranth HDL
missing-semester-cn.github.io
the CS missing semester Chinese version
mtkcpu
RiscV CPU implementation in Amaranth HDL (aka nMigen)
openc906
OpenXuantie - OpenC906 Core
openc910
OpenXuantie - OpenC910 Core
opene902
OpenXuantie - OpenE902 Core
opene906
OpenXuantie - OpenE906 Core
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
transformer
Transformer: PyTorch Implementation of "Attention Is All You Need"
transformers
🤗 Transformers: State-of-the-art Machine Learning for Pytorch, TensorFlow, and JAX.
verilog-axi
Verilog AXI components for FPGA implementation
wujian100_open
IC design and development should be faster，simpler and more reliable
yosys
Yosys Open SYnthesis Suite
zhoushan
Open Source Chip Project by University (OSCPU) - Zhoushan Core
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