hansungk Goto Github PK
Name: Hansung Kim
Type: User
Company: UC Berkeley EECS
Location: Berkeley, CA
Hansung Kim's Projects
androidpts
Pitch Tracking System ported to Android, for those who wouldn't happily pay 300 million $ to use the old one.
awesome-go
A curated list of awesome Go frameworks, libraries and software
beat-detector
A Clojure audio beat detection library
bitbuf
Fast and easy bit wrangling in C++
chacom-ds
Data structure lecture files from Cha's Happy Computer Programming
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
circuit-prelabs
Prelab reports for SNU 2015-1 Basic Circuit Theory class
conf
Various configuration files for my Linux setup.
gemmini
Gemmini updated to match Einstein config
gemmini-rocc-tests
Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator
globe
Clojure Minecraft world file wrangler
javapts
Just a Java testbed for androidPTS development
lcc
The lcc retargetable ANSI C compiler
lilypond-sheets
Lilypondify them all songs
llvm-build
My personal cmake build shell scripts
mono
Mono open source ECMA CLI, C# and .NET implementation.
netsim
Simple event-driven interconnection network simulator
opengl-tut
OpenGL tutorials and tests
pocl
a clone of POCL that includes RISC-V newlib devices support and Vortex
programming-clojure
Scratch codes written while reading Programming Clojure, 2e
qemu
Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
radpie
Simple DPI memory fuzzer module/library
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-opcodes
RISC-V Opcodes
rocket-chip
Manual fork of chipsalliance/rocket-chip
ruse
toy compiler
simplescalar-smt
SimpleScalar simulator modified to support simultaneous multithreading
snu-data-structure
Exercise source files for the SNU ECE Data Structure class
tf2-configs
Junk TF2 scripts I use.
tsc-cpu
Simple in-order pipelined CPU implementation using TSC ISA for SNU ECE430.322 ComOrg
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