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Murali Gullapalli's Projects

asynchronous-fifo-design-automation-using-tcl icon asynchronous-fifo-design-automation-using-tcl

Working in automating the asynchronous FIFO with increased address space. Using TCL to write procedures like checking logic levels in critical path, critical path transitions, purposeful skew procedures etc. The scope of the project can be further extended to automate designs like MIPS and RISC V architectures.

design-and-verification-of-ddr3-sdram-memory-controller icon design-and-verification-of-ddr3-sdram-memory-controller

Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for setting up the interfaces and writing tasks for various operations. Performed randomized, Constrained, and directed test cases to validate our DUT.

silumation-and-verification-of-last-level-l2-cache icon silumation-and-verification-of-last-level-l2-cache

Simulated a 16MB 8-way set associative last level cache following write allocate policy employing MESI protocol in order to maintain cache coherence and inclusivity. Used pseudo LRU as the replacement policy. Have used multiple trace files to drive the inputs to test our cache model

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