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code,code,code.

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amba_axi3

System Verilog and Emulation. Written all the five channels.

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

awesome-systemc-ams

A curated list of SystemC-AMS resources

axi_spec_chinese

AXI协议规范中文翻译版

gem5-gpu

learnsystemc

Learn systemC with examples

verilator

Verilator

xdupgthesis

[停止维护 请使用note286/xduts]西安电子科技大学研究生学位论文XeLaTeX模板