Comments (15)
@proppy : Yes, LVPWELL outside of DNWELL is equivalent to substrate and should be treated as such. That usage is in much of the GF IP.
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Thanks @RTimothyEdwards
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@RTimothyEdwards Thanks for the explanation.
@atorkmabrains would it makes sense to update the pcells to always draw LVPWELL
when Bulk Tie
is set?
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@msaligane - this was the issue I was talking about - We had to add Deep N well as a fix to pass LVS because the bulk pin would not get connected appropriately if DN WELL was not enabled
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@atorkmabrains currently it seems that LVPWELL
is only drawn when DNWELL
is set in the pcell option, would it make sense to update the pcell implementation to always draw LVPWELL
when bulk tie is enabled independently of the state of the DNWELL
option?
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@proppy That's a separate issue. LVPWELL
is optional or don't care in case that DNWELL
is not drawn. If you draw, DNWELL
you can draw LVPWELL
. Pcell is functioning correctly, no need to add this modification into the pcell.
@spnadig Could you please show me the design that caused this?
I advise that you use DRC and LVS from https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr? Also, please stay tuned as we are going to move LVS and DRC to: https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pv.
cc @msaligane
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@RTimothyEdwards Thanks for the explanation.
@atorkmabrains would it makes sense to update the pcells to always draw
LVPWELL
whenBulk Tie
is set?
@proppy No, as I mentioned in my comment above, LVPWELL
is totally ignored in everything if there is no DNWELL
. No need to modify the pcell.
The issue that @spnadig is having is a separate issue. I need to look into it.
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My understanding is that in #104 (comment) @RTimothyEdwards stated that LVPWELL
without DNWELL
was a valid usecase.
Shouldn't we make sure that this is also supported by the pcell?
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@proppy yes, you could draw LVPWELL
but the correct action is to not to draw it by default as it's disregarded in case the DNWELL
is not drawn. The pcell is designed to allow the real
use case of the LVPWELL
. I don't advise to add LVPWELL
if you are not really using it.
An exception to my comment above is the standard cells, standard cells should have LVPWELL
just in case the user might want to use DNWELL
later around the digital block later for any electrical reasons. But this use scenario is only valid for standard cells.
As for @RTimothyEdwards comments, what he basically wanted to say if I understand it correctly, is that LVPWELL
is disregarded and we shall consider it as if it's not even drawn if it doesn't reside inside DNWELL
and consider LVPWELL
as part of the regular silicon substrate.
@RTimothyEdwards Please correct me if you think my comment above doesn't match yours.
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@proppy I'm more concerned about the issue highlighted by @spnadig regarding the LVS. I need to understand that use case and why it didn't pass without DNWELL
even if the LVPWELL
is present. This has nothing to do with the pcell adding LVPWELL
rather it's related to the LVS rule deck.
@spnadig Please share a test case and open an issue saying LVS doesn't pass due to LVPWELL
. That might be a problem that we might need to fix.
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@atorkmabrains I think this is due to the substrate connection of the bulk tie creating an additional signal (gf180mcu_gnd
) when the LVPWELL
is not present.
Is there a usecase for setting Bulk tie
without drawing LVPWELL
?
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@proppy bulk tie
doesn't need LVPWELL
to happen, please read here:
https://en.wikipedia.org/wiki/CMOS
And BTW, that's the normal in almost all CMOS processes.
GF180MCU
is a triple well technology, hence we need a PWELL
marker:
https://www.researchgate.net/figure/Triple-well-NMOS-transistor-structure-See-the-colors-in-the-online-version_fig2_303530652
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bulk tie doesn't need LVPWELL to happen, please read here: https://en.wikipedia.org/wiki/CMOS
Thanks for providing the links, I could find any mention of bulk tie
nor its relation (if any) to PWELL
on it, do you have an alternative source of documentation?
GF180MCU is a triple well technology, hence we need a PWELL marker:
https://www.researchgate.net/figure/Triple-well-NMOS-transistor-structure-See-the-colors-in-the-online-version_fig2_303530652
Without a PWELL
it seems that the current LVS extraction is not able to infer the substrate connection of the BULK
tied to SRC
terminal for nmos device effectively leaving it floating with a different ground net, is that intentional? Or is there a different way to provide a hint for this implicit connection in the layout?
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Without a
PWELL
it seems that the current LVS extraction is not able to infer the substrate connection of theBULK
tied toSRC
terminal for nmos device effectively leaving it floating with a different ground net, is that intentional? Or is there a different way to provide a hint for this implicit connection in the layout?
If what you mentioned is true that LVS requires LVPWELL
to get the connectivity to substrate, then that's definitely a bug in LVS. I need the test case that has that issue. Also, are they using Google repo? If yes, then please tell them to use efabless one as Google repo is not updated and not cleaned.
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bulk tie doesn't need LVPWELL to happen, please read here: https://en.wikipedia.org/wiki/CMOS
Thanks for providing the links, I could find any mention of
bulk tie
nor its relation (if any) toPWELL
on it, do you have an alternative source of documentation?
As for your question about this, you need to know more about micro-electronics bulk tie
has many different words that represent it, you don't necessarily need to find in the link I provided. Here are a few good courses you could start looking at:
- https://ocw.mit.edu/courses/6-012-microelectronic-devices-and-circuits-fall-2005/pages/lecture-notes/
- http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee240_sp12/lectures.html
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Related Issues (20)
- Please fix cells/xschem/symbols/vnpn_10x10.sym: S (substrate) terminal incorrectly named B HOT 1
- lvs script should be able to import xschem netlist HOT 4
- CI runs is complaining about "`set-output` command is deprecated" HOT 4
- DRC PL.2_3.3V mixes gate length rules with gate width rules HOT 3
- Update Google repo with the latest updates in Efabless Version
- nfet_03v3_dw missing in PDK? HOT 3
- Typo in LVS command line arguments checking "--net" HOT 1
- Fix `gf180mcuC` `xschemrc`
- SPICE Model refactoring HOT 1
- parameter m (multiplier) in GF180mcuc PDK not working
- Missing 5V transistor in transistor models set for GF180 MCU HOT 7
- Layer map confusion regarding GF180 MCU top layer and metal 5 mapping. HOT 3
- NMOS/PMOS Pcell non symetrical
- CI fails with issue around qt5-default HOT 1
- Warnings from the `actions/setup-python@v3` GitHub Action on CI HOT 8
- incorrect symbol path in xschem tests
- Transient noise simulation in Ngspice HOT 1
- Issue with GF180 PDK and symbols import into Xschem and incompatibility with definitions in sm141064.spice HOT 11
- lvs script should be able to read X subcircuit HOT 1
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