"make load" step got stuck about cfu-playground HOT 5 OPEN

I find out that if I comment this line assign cfu0 = (neg << 16) + degree2; or change it to assign cfu0 = 32'b0;, it works. Weird! Why?

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Well, I've changed my cfu.v and got this in my terminal.

make[3]: Leaving directory '/home/limx/CFU-Playground/soc'
/home/limx/CFU-Playground/soc/bin/litex_term --speed 1843200  --kernel /home/limx/CFU-Playground/proj/fft/build/software.bin /dev/ttyUSB1

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 BIOS built on Feb  5 2023 22:07:56
 BIOS CRC failed (expected %x, got 0x4e20f513)
 The system will continue, but expect problems.

Then, it will print messy code.

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Hi @limingxuan-pku ; hmm, these symptoms point to some part of the circuit not meeting timing and therefore corrupting data. It looks like you are using Arty A7 board and the SymbiFlow / F4PGA toolchain, am I correct?

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Hi @limingxuan-pku ; hmm, these symptoms point to some part of the circuit not meeting timing and therefore corrupting data. It looks like you are using Arty A7 board and the SymbiFlow / F4PGA toolchain, am I correct?

Yes, I use Arty A7 and SymbiFlow, working environment is Virtual Machine Ubuntu 20.04. So could you please teach me how to recognize and avoid such timing issues?

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Hi @limingxuan-pku ---

The files generated by SymbiFlow/F4PGA will be in $CFU_PLAYGROUND/soc/build/digilent_arty.<projname>/gateware/. In there, you can look at report* files, for example report_timing.setup.rpt.

But now that I'm looking at the files, I can't figure out where the requested 75MHz clock (from LiteX) is being passed to the F4PGA tools. Specifically, the .sdc file is empty, and I don't see anything like a create_clock command in the .xdc file.

@kgugala who can I ask for more info here?

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