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basic_verilog

Must-have verilog systemverilog modules

bodh1.0

register auto generate from excel file

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

e203_hbirdv2

The Ultra-Low Power RISC-V Core

gaia

Generate UVM testbench framework template files with Python 3

gitcyan.github.io

Build a Jekyll blog in minutes, without touching the command line.

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

ncovmemory

2020新冠肺炎记忆：报道、非虚构与个人叙述（持续更新） Memory of 2020 nCov: Media Coverage, Non-fiction Writings, and Individual Narratives (Continuously updating)

nyuziprocessor

GPGPU microprocessor architecture

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

pytools

useful Python scripts for learning and exercise

sudokupyworks

A Sudoku game written in Python as an exercise miniproject for Python learning.

tools_padringautocheck

uvm-python

UVM 1.2 port to Python

uvm-tutorial-for-candy-lovers

Source code repo for UVM Tutorial for Candy Lovers

uvm_axi

uvm AXI BFM(bus functional model)

uvm_tb_gen

generate UVM testbench using python

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

uvmreference

Reference examples and short projects using UVM Methodology

wavedrom

:ocean: Digital timing diagram rendering engine

wujian100_open

IC design and development should be faster，simpler and more reliable

xilinxtclstore

Xilinx Tcl Store

yosys

Yosys Open SYnthesis Suite