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Name: George.Guang
Type: User
Bio: Type faster Work harder
Location: Shenzhen city, China
Name: George.Guang
Type: User
Bio: Type faster Work harder
Location: Shenzhen city, China
This repository contains a step by step procedure to the complete RTL2GDSII flow of PICORV32A RISC-V core design using open-source EDA tool OpenLANE and Google-Skywater’s first manufacturable open source 130nm PDK.
This repository contains the details of steps followed and summary of hands on done on doing the Advanced Physical Design Using OpenLANE/SKY130 workshop. The workshop focuses on complete ASIC Design flow from RTL2GDS using Open Source EDA tool OpenLANE and Google SKYWater130nm pdk. The core of design PICORV32A used is of RISC-V architechture.
This repository contains all the information studied and created during the Advanced Physical Design Using OpenLANE / SKY130 workshop. It is primarily focused on a complete RTL2GDS flow using the open-source flow named OpenLANE. PICORV32A RISC-V core design is used for the purpose.
This Repository mainly created to focus on the work-done in 5 Days workshop of Adavance Physical Design using OpenLANE/SkyWater130. The Workshop mainly focus on to hands on experience of the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
A curated list of spec, maturity comparison between current Open RISC-V cores.
An AXI4 crossbar implementation in SystemVerilog
32-bit Superscalar RISC-V CPU
Hardware Scheduled Dual Core RISC-V (OOO IMAC + Pipelined IA) Processor with a snoop bus interconnect (MESI Protocol) -- all in SystemVerilog
:milky_way: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Quad cluster of RISC-V cores with peripherals and local memory
Basic floating-point components for RISC-V processors
CORE-V Family of RISC-V Cores
Functional verification project for the CORE-V family of RISC-V cores.
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
Another tiny RISC-V implementation
Processor support packages
VeeR EH1 core
CHIPSALLIANCE Cores-VeeR-EH2
VeeR EL2 Core
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
National French competition for optimizing the power consumption of an Application class 6-stage RISC-V CPU (CORE-V CVA6)
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A declarative, efficient, and flexible JavaScript library for building user interfaces.
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TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. 📊📈🎉
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google ❤️ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.