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100g-verilog-rocev2-lite

TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.

alpide_carrier

Carrier of an ALPIDE chip mounted on an Arduino Shield.

alveo-pynq_ml

Neural network inferences on Alveo cards with hls4ml framework

base2_log

Hardware implementation of a base 2 logarithm

fast_crc32

CRC computation entirely in VHDL with a generic polynomial.

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fpga_projects

Some of my projects/mistakes on various FPGA boards

gabriele-bot

gt-final-or

VHDL files of the phase-2 Global Trigger monitoring

hls4ml

Machine learning in FPGAs using HLS

lab-repository

mapd_lab

master_thesis_gb

mos_capacitor_calculator

Mos capacitor band diagram calculator.

phase2-l1menutools

This repository contains the framework for the measurement of matching efficiencies, trigger turn-on curves, and scalings for the assessment of the physics performance of the CMS Phase-2 L1 Menu.

pynq_ia

Repository that contains some neural network inferences on PYNQ-Z2 board employing hls4ml

verilog-ethernet

Verilog Ethernet components for FPGA implementation