doudouli12 Goto Github PK
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doudouli12's Projects
ahb-sramc
IC Verification & SV Demo
ahb-to-apb-bridge-verification
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
ahb2apb-bridge
An uvm verification env for ahb2apb bridge
ahb_sramc
ahb scram controller, design and verification
alu-verification-environment
Development UVM Verification Environment for ALU DUT
alu_tb
Basic ALU testbench written in UVM for experiments
alu_verification_ip
Verification IP for ALU written using SystemVerilog (UVM)
amba_apb_sram
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
apb_vip
Verification IP for APB protocol
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi4_vip
Verification IP for APB protocol
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cpu8080-alu
UVM code to verify ALU
fifo_verification-
fifo verification IP using system verilog
fpga-support
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
i2c_vip
Verification IP for I2C protocol
lm-riscv-dv
An Open-Source Design and Verification Environment for RISC-V
logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
mpsoc-dv
MPSoC verified with UVM/OSVVM/FV
opentitan
OpenTitan: Open source silicon root of trust
poc
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
pulpino_soc_uvm_testbench
UVM testbench for verifying the Pulpino SoC
python
My Python Examples
python-100-days
Python - 100天从新手到大师
python_1
Python3编写的各种大小程序，包含从零学Python系列、12306抢票、省市区地址库以及系列网站爬虫等学习源码
risc_verif_demo_0
a very simple risc_cpu verification demo with uvm
riscv
RISC-V CPU Core (RV32IM)
riscv-formal
RISC-V Formal Verification Framework
riscv-vip
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
single-cycle-processor
Single-Cycle RISC-V Processor in systemverylog
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